// File: dff.v
// Generated by MyHDL 0.8dev
// Date: Wed Apr 25 18:41:03 2012


`timescale 1ns/10ps

module dff (
    q,
    d,
    clk
);


output q;
reg q;
input d;
input clk;






always @(posedge clk) begin: DFF_LOGIC
    q <= d;
end

endmodule
